There is a continuing demand for semiconductor memory devices with higher density and low power consumption. Semiconductor memory devices include, for example, SRAM and DRAM (dynamic random access memory) devices. Although DRAM provides a high degree of integration, SRAM is typically preferred over DRAM because SRAM cells can operate at higher speeds and lower power dissipation than DRAM cells. Indeed, SRAM cells typically do not require refreshing and can store data indefinitely as long as such cells are powered. In contrast, DRAM cells must be periodically refreshed.
One well-known conventional structure of an SRAM cell is a 6T (six transistor) cell that comprises six MOS (or FET) transistors. Briefly, a 6T SRAM cell comprises two cross-coupled inverters that form a latch circuit. The latch is connected between power and ground and is connected to a pair of access transistors. Each inverter comprises two transistors (typically an NMOS pull-down transistor and pull-up PMOS transistor). The latch, which is formed by the first and second cross-coupled inverters, is connected between two storage nodes, wherein one of the storage nodes is pulled low and the other storage node is pulled high. Each storage node is connected to a bit line or complementary bit line of a bit line pair via an access transistor. The gate terminals of the access transistors are commonly connected to a wordline. When the access transistors are deactivated, the storage nodes are essentially insulated from the bit lines, although some leakage can occur.
Although 6T SRAM cells can provide high speed operation and can operate with low power supply voltage, 6T cells occupy a large area, thus limiting the memory cell density. Accordingly, to provide higher density SRAM memory, 4T SRAM cell architectures such as loadless 4T SRAM cells, have been proposed, which occupy significantly less space than 6T SRAM cells.
For example, FIG. 1 illustrates a conventional loadless 4T SRAM cell. In general, the loadless 4T cell (10) comprises a CMOS memory cell that uses four transistors, wherein no load elements are connected to storage nodes of the cell. More specifically, as depicted in FIG. 1, the loadless 4T SRAM cell (10) comprises four-transistors including two access transistors (P1) and (P2) (or pass transistors) and two pull-down transistors (D1) and (D2) or (drive transistors). The access transistors (P1) and (P2) are PMOS transistors and the pull-down transistors (D1) and (D2) are NMOS transistors. A wordline (WL) is commonly coupled to the gates of the access transistors (P1) and (P2). A bit line pair connected to the memory cell (10) comprises a complimentary bit line (/BL) and a bit line (BL). The bitline (BL) is connected to the source of access transistor (P1) and the complementary bit line (/BL) is connected to the source of access transistor (P2). The drain of access transistor (P1) is connected to storage node (S1) and to the gate of pull-down transistor (D2). The drain of access transistor (P2) is connected to storage node (S2) and to the gate of pull-down transistor (D1). The drain of access transistor (P1) is connected to the source of pull-down transistor (D1) and the drain of pull-down transistor (D1) is connected to ground (or Vss). Similarly, the drain of access transistor (P2) is connected to the source of pull-down transistor (D2) and the drain of pull-down transistor (D2) is connected to ground (or Vss).
When the storage node (S1) is at logic “1” and the storage node (S2) is at logic “0”, the cell (10) can be considered as storing a logic “1”. In contrast, when the storage node (S1) is at logic “0” and the storage node (S2) is at logic “1”, the cell (10) can be considered as storing a logic “0”. Thus the cell (10) is bistable, i.e., the cell (10) can have one of two stable states, logic “1” or logic “0”.
In contrast to conventional 6T SRAM cells with pull-up transistors or 4T SRAM cells with resistive loads, a loadless SRAM (as shown in FIG. 1) does not have loads that are connected between the storage nodes (S1) and (S2) and power supply (e.g., Vdd), which provides the current needed to maintain the state of the latch. Instead, the data state of the loadless 4T cell (10) is maintained by leakage current provided by the access transistors (P1) and (P2). For this purpose, the conventional loadless 4T SRAM cell (10) uses PMOS access transistors (P1) and (P2) to supply the leakage current needed to maintain the data state of the latch circuit during “standby” (i.e., when the cell is not accessed).
More specifically, the loadless 4T SRAM memory cell (10) operates as follows during standby. Assume that storage node (S1) is at a voltage potential of logic “1” and that storage node (S2) is at a voltage potential of logic “0”. In this instance, the pull-down transistor (D1) and access transistor (P1) are turned “off” because the gate of pull-down transistor (D1) is logic “0” and the WL (connected to the gate of access transistor (P1) is not activated. In this state, without the leakage current through the access transistor (P1), the potential of storage node (S1) can gradually decrease due to a subthreshold leakage current through the pull-down transistor (D1). Although the loadless 4T memory cell (10) has no load element connected between a power supply and node (S1) for supplying current to the storage node (S1), the leakage current of the PMOS (or PFET) access transistor (P1) flows to the storage node (S1) to compensate for the depletion of charge from the storage node (S1).
To sufficiently maintain the data state (e.g., substantially maintain a logic “1” at node (S1) in the above example), the leakage current that flows from the access transistor (P1) into the storage node (S1) should be greater than the leakage current through the pull-down transistor (D1) which connects node (S1) to ground (or Vss). The conventional loadless SRAM cell (10) as shown in FIG. 1 utilizes PMOS (or PFET) access transistors (P1) and (P2) because such transistors are leakier than NMOS (or NFET) transistors and thus, provide the necessary leakage current to maintain a logic “1” that is stored at node S1 or S2. Another reason PMOS access transistors are used in the conventional architecture is that such transistors conduct a logic “1” very well, as compared to NMOS transistors where a logic “1” is decreased by the voltage threshold (Vt) of the access transistor. In other words, with PMOS access transistors, a logic “1” can be read from and written to the cell without a voltage drop of Vdd-Vt.
An advantage of the loadless 4t memory cell (10) is that it eliminates the need for providing load elements that are generally connected to the storage nodes of the pull-down transistors, thereby simplifying the structure of the memory cell. However, a disadvantage associated with the loadless SRAM cell (10) of FIG. 1 is that the PMOS or PFET access transistors (P1) and (P2) are relatively larger as compared to NMOS or NFET devices, which can limit the cell density. Furthermore, PFETs have slower switching speeds as compared to NFETs of the same geometry. Thus, the use of PFET access transistors in the loadless 4T cell (10) of FIG. 1 decreases the access speed of the cell. Indeed, the carrier mobility of a PFET is about one-half (½) of that of an NFET and therefore, to obtain the same switching performance as that of an NFET, the channel width of a PFET access device would have to be increased 2×.
Therefore, there is a need for an improved architecture for a loadless, 4T SRAM cell, and method of operating such SRAM cell, which would provide increased performance and density than that of conventional loadless 4t SRAM cells.